This invention is generally directed to finite state machines implemented in a microcomputer having memory in which logical expressions are stored. This invention is specifically directed to such an implementation wherein sets of logical vectors can be stored in a flexible arrangement in which different numbers of such vectors are permitted for different states of a finite state machine.
As used herein, a finite state machine refers to a sequential system in which input parameters determine the state of operation of the machine. An implementation of a finite state machine is described in U.S. Pat. No. 5,301,100, entitled "Method of an Apparatus for Constructing a Control System and Control System Created Thereby". This patent describes a logic table for implementing the finite state machine in which a specific fixed organization of data represents application logic conditions expressed utilizing logical AND and OR operators. FIGS. 1-7 in the present application describe aspects of such a prior art finite state machine implementation.
The above referenced prior art implementation of a finite state machine is encoded in a fixed size data structure in which logical vectors are stored in memory to define changes in output actions and change of state transitions in the finite state machine. The fixed coding arrangement requires that the maximum number of logical vectors utilized for a given set of conditions be utilized for the other sets of like conditions. This results in individual vectors which are blank, i.e. contain no logical data, since each fixed memory allocation must reflect the maximum possible number of vectors. Thus, there exists a need for an improved implementation of a finite state machine which minimizes memory usage.